The present invention pertains to the technical field of DA converters and AD converters, and more specifically, it pertains to high-precision DA converters and AD converters.
Frequency synthesizers with discrete frequency divider PLL (phase lock loop) circuits are furnished with a compensation circuit, which compensates for ripple current present in the PLL control signals used for the internal control of the PLL circuits by adding a compensating current to the PLL control signals.
This compensation circuit has a capacitor and a DA converter. When digital data are input, the digital data undergo DA conversion by means of the DA converter, an analog voltage of a magnitude corresponding to the digital data is generated and impressed on the capacitor, and compensating current is added to the control signals by means of the charging and discharging of the capacitor. The precision of the compensating current depends on the precision of the DA converter, so it is preferable if the compensation circuit contains a high-precision DA converter.
A conventional R-2R type DA converter is indicated by symbol 110 in FIG. 4 as a DA converter. This DA converter 110 has standard voltage input terminal 120 and output terminal 130, as well as two terminating resistors 1141 and 1142, multiple unit resistors 111, weighting resistors 112, and switching circuits 113.
The multiple unit resistors 111, the multiple weighting resistors 112, and the terminating resistors 1141 and 1142 all have the same resistance values respectively.
Switching circuits 113 each have standard voltage terminal 115, ground potential terminal 116, switch terminal 117, and control terminal 118. They are designed so that when a signal is input to control terminal 118, switch terminal 117 can be connected to either standard voltage terminal 115 or ground potential terminal 116. Standard voltage terminal 115 is supplied with the standard voltage via standard voltage input terminal 120 and ground potential terminal 116 is supplied with ground potential, and switch terminal 117 can be connected to either the standard voltage or to ground.
The switching circuits 113 are laid out toward the ground potential connection from the output terminal 130, wherein the output terminal 130 is connected to the very first stage and the ground potential is connected to the very last stage. Here, there are 14 switching circuits 113. They are numbered in increasing order starting from output terminal 130 toward the ground potential connection, wherein switching circuits 1131-11314 are arranged starting at output terminal 130 toward ground.
One weighting resistor 1121-11214 is within each switching circuit 1131-11314, and one end of weighting resistors 1121-11214 is connected to switch terminal 1171-11714 of switching circuits 1131-11314.
The other end of weighting resistor 1121 within first-stage switching circuit 1131 is connected to output terminal 130, and the other end of weighting resistor 11214 within last-stage switching circuit 11314 is connected to ground via one terminating resistor 1142. The other terminating resistor 1141 is placed between output terminal 130 and ground.
The resistance value of weighting resistors 112 is set to twice the resistance value of unit resistors 111, and the resistance value of terminating resistors 114 is also set to twice the resistance value of unit resistors 111.
When the standard voltage is divided by aforementioned DA converter 110 to produce a magnitude that corresponds to the digital data; in other words, performing DA conversion, each bit of digital data is supplied to control terminals 114 as a signal that controls switching circuits 113 and a standard voltage Va is impressed on standard voltage input terminal 120.
Each switching circuit 113 connects switch terminal 117 either to standard voltage Va or to ground according to the signal input to control terminal 114. Here, when the signal input to control terminal 114 is xe2x80x9c1,xe2x80x9d switch terminal 117 is connected to standard voltage Va, and when xe2x80x9c0,xe2x80x9d switch terminal 117 is connected to ground.
In this case, 13 unit resistors 111 are furnished, and they are numbered in increasing order from output terminal 130 toward the ground potential connection, wherein the unit resistors 111 consist of unit resistors 1111-11113. One end of unit resistor 1111 is connected to output terminal 130 and one end of unit resistor 11113 is connected to ground via terminating resistor 1142.
Weighting resistors 1121-11213 and switching circuits 1131-11113 are connected to one end of unit resistors 1111-11113, respectively. Each switching circuit 1131-11314 has a control terminal 1181-11814. The bits of the digital data from most significant bit to least significant are input to the control terminals 1181-11814, respectively.
In this case, N1-N14 are values of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d that correspond to each bit of the 14-bit digital data, wherein N1 and N14 are values that correspond to the most significant bit and the least significant bit, respectively. From output terminal 130 of DA converter 110, an output voltage VO of a magnitude corresponding to the digital data is output such that:   Vo  =            (              1        /        3            )        xc3x97    Va    xc3x97          {                                    N            ⁢                          (              1              )                                xc3x97                                    (                              1                /                2                            )                        0                          +                              N            ⁢                          (              2              )                                xc3x97                                    (                              1                /                2                            )                        1                          +                              N            ⁢                          (              3              )                                xc3x97                                    (                              1                /                2                            )                        2                          +                              N            ⁢                          (              4              )                                xc3x97                                    (                              1                /                2                            )                        3                          +        …        +                              N            ⁢                          (              13              )                                xc3x97                                    (                              1                /                2                            )                        12                          +            
If the resistance values of weighting resistors 1121-11213 and the resistance values of terminating resistors 1141 and 1142 are equal to twice the resistance value of unit resistors 1111-11113, a standard voltage Va can be divided equally into minimum steps 1/3xc3x97Vaxc3x971/213 in order to output the output voltage VO, wherein an output voltage VO with a magnitude corresponding to the digital data can be output for equal intervals of the range 0-Va.
However, with the DA converter 110 mentioned above, when the resistance values of unit resistors 1111-11113 and weighting resistors 1121-11214 are different relative to each other, the standard voltage Va will not be divided into equal intervals over the range 0-Va. Particularly when the digital input signal is incremented by one, the output voltage immediately after the incremented digital signal is input will be excessively large, and there is the problem that the voltage difference with the output voltage immediate before the digital signal is incremented is a large, so there is a large error, and the precision of DA conversion will decrease.
The present invention was devised to solve the aforementioned problems of the prior art. Its purpose is to offer a high-precision DA converter and an AD converter that use the present invention.
In order to solve the aforementioned problems, the invention described herein offers a DA converter that has n switching circuits equipped with: a first input terminal, a second input terminal, a control terminal, and a switch terminal, which can be connected to the aforementioned first input terminal or the aforementioned second input terminal according to the signal input to the aforementioned control terminal; (nxe2x88x921) first-value resistors connected in series; n second-value resistors, which are each connected at one end to the aforementioned switch terminals of the aforementioned n switching circuits; first and second third-value resistors connected between one end of the first first-value resistors and a standard voltage and between end of the (nxe2x88x921)th first-value resistors and the aforementioned standard voltage, respectively; standard voltage input terminals connected to each first input terminal of the aforementioned n switching circuits; and an output terminal connected to the mid-point of the connection between one end of the first of the aforementioned first-value resistors and the aforementioned first third-value resistor and to the other end of the first of the aforementioned second-value resistors. The other end of the second to (nxe2x88x921)th of the aforementioned second-value resistors is connected to the mid-point of the connection between the other end of the kxc2x1h (k=1 to (nxe2x88x922)) first-value resistors and the aforementioned end of the (k+1)th first-value resistors, and the other end of the nth second-value resistors is connected to the mid-point of the connection of the other end of the (k+1)th first-value resistors and the aforementioned second third-value resistor. Each second input terminal of the aforementioned n switching circuits is connected to the aforementioned standard voltage. The resistance value of the aforementioned first-value resistors, the aforementioned second-value resistors, and the aforementioned third-value resistors is Rxe2x88x92xcex94R, 2R+xcex94R, and 2Rxe2x88x92xcex94R, respectively (xcex94R is the resistance value error for a resistance value R).
Also, another embodiment of the invention offers a sequential comparison type AD converter that has a DA comparator as described above.
With the DA converter of the present invention, the resistance value of the weighting resistors (second-value resistors) is set to twice the resistance value of the unit resistors (first-value resistors). As an example, the resistance value of the unit resistor is set to a value wherein a small resistance value error (xcex94R) relative to a standard resistance value is subtracted from the unit resistance value (R). The resistance value of the weighting resistor is set to a value calculated by adding the resistance value error to twice the standard resistance value. The resistance value of the terminating resistor (third-value resistor) is set to a value wherein the resistance value error is subtracted from twice the standard resistance value.
By setting the resistance value of each resistance in this way, when a digital data signal is incremented even if the output voltage immediately before the digital signal is incremented is larger than the output voltage immediately after the digital signal is incremented, the output voltage immediately after the digital signal is incremented will not be excessively large compared to the output voltage immediately after the digital signal is incremented. So even if the resistance value varies so that the difference in voltage between the output voltage immediately before the digital signal is incremented and the output voltage immediately after the digital signal is incremented is large, the voltage difference between the output voltage immediately before the digital signal is incremented and the output voltage immediately after the digital signal is incremented will be smaller than in the past.
Thus, error with DA conversion caused by the voltage difference of the output voltage immediately before the digital signal is incremented and immediately after the digital signal is incremented will be small, and a DA conversion with higher precision than in the past can be realized.
Also, the appropriate resistance value error can be set according to the predicted variation in resistance values between the resistance value of the weighting resistor and the resistance value of the unit resistor, so that, when a large variation in resistance values is predicted, the resistance value error is set to a larger value, and when a small variation is predicted, the resistance value error is set to a smaller value.